Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion

A new approach to handle the inductance effect on multiple signal lines is presented. The worst case switching pattern is first identijied. Then a numerical approach is used to model the effective loop inductance (Leg) for multiple lines. Based on look-up table for Leg, an equivalent single line model can be generated to decouple a specific signal line from the others to per$orm static timing analysis. Compared to the use of f i l l RLC netlist for multiple lines, this approach greatly improves the computation eficiency and maintains accuracy for timing and signal integrity analysis. Applications to repeater insertion in the critical path chains are demonstrated. For a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, w e j n d that same number of repeaters is inserted for optimal delay according to both the RC and RLC multiple line models. With increasing chip size and the number of data bits, many long global lines run in parallel in the same layer. Besides metal-to-ground capacitance (C,) and selfinductance (L.q), coupling capacitance (C,) and mutual inductance (L,) are also important for correct delay and noise estimation. In the RC line model, the orthogonal layer can approximately be treated as a ground plane for capacitance coupling simulation [7]. Since C, drops quickly with increasing spacing, the nearest neighboring lines (first neighbors) will see the most of the charge excited by the aggressor. Other farther neighboring lines (second and the higher order neighbors) contribute minimally to capacitance coupling. In this sense, capacitance coupling is a 'short range' effect, and we only need to include the first neighbors into delay and noise calculation. Fig. l a shows the dominant 'charge sharing' path for capacitance coupling (C,+ C,). The 1'' neighbors shield most of the capacitance coupling from higher order neighbors. 1'' neighbors Aggressor I \ /